The present invention relates generally to the fabrication of semiconductor devices, and more particularly to methods and structures that implement air gaps in semiconductor devices.
As device dimensions continue to shrink, a reduction in interconnect linewidths leads to increased line resistance (R) for signals. Further, reduced spacing between conducting lines creates more parasitic capacitance (C). The result is an increase in RC signal delay, which slows chip speed and lowers chip performance.
The line capacitance, C, is directly proportional to the dielectric constant, or k-value of a dielectric material. A low-k dielectric reduces the total interconnect capacitance of the chip, reduces the RC signal delay, and improves chip performance. Lowering the total capacitance also decreases power consumption. The use of a low-k dielectric material in conjunction with a low-resistance metal line provides an interconnect system with optimum performance for the ULSI technology. For this reason, prior art attempts to reduce the RC delays have focused on utilizing material with a low-k to fill the gaps between the metal lines. Silicon dioxide (SiO2) has been conventionally preferred as a dielectric material even though it has a relatively high dielectric constant (relative to vacuum) of about 4.1 to 4.5 because it is a thermally and chemically stable material and conventional oxide etching techniques are available for high-aspect-ratio contacts and via holes. However, as device dimensions decrease and the packing density increases, it is necessary to reduce the spacing between conductive lines to effectively wire up the integrated circuits. Therefore, a large number of lower dielectric constant materials are currently being investigated to reduce the RC value of the chip further. These include among many others fluorinated SiO2, aerogels, and polymers. Another method being proposed to lower the dielectric constant even further is to form air gaps between the interconnect lines. While silicon dioxide has a dielectric constant of about 4 and greater, the dielectric constant of air is about 1.
The formation of air gaps between conducting lines of high speed integrated circuits (IC's) is typically a combination of the deposition of a porous dielectric layer, selective etching of the dielectric layer, the deposition of a metal layer, and the removal of the dielectric layer to form the desired air gaps.
U.S. Pat. No. 5,407,860 (Stoltz et al.) discloses an air gap process by etching low-k material out between metal lines and forming a dielectric layer thereover.
U.S. Pat. No. 5,444,015 (Aitken et al.) shows a method for forming air gap between metal lines by removing the dielectric material between the lines.
U.S. Pat. No. 5,324,683 (Fitch et al.) shows a method for forming an air gap between metal lines by forming a dielectric layer between metal lines, forming an etch barrier layer(s) thereover and opening a hole in the etch barrier layer and isotropically etching the dielectric layer for form air gaps.
Although air is the best dielectric material for lowering the RC value, unfortunately the use of air gap structures in integrated circuit fabrication has been hindered with problems. Overall mechanical strength of the device is reduced correspondingly and lead to structural deformation and a weakened structure can have serious effect in various aspects of subsequent integrated circuit fabrication. To illustrate, FIG. 1 depicts a cross sectional view of a portion of an interconnect structure having air gaps formed therein according to a conventional method of interconnect formation. A semiconductor substrate 10 has a patterned barrier layer 20 formed thereon. A plurality of metal lines 80 are interposed between portions of the barrier layer 20 with air gaps 90 formed therebetween. A barrier layer 100 seals the upper surfaces of the plurality of metal lines 80 and air gaps 90. A dielectric layer 120 is subsequently formed above the barrier layer 100. While a portion of dielectric layer 120 overlying barrier layer 100 may not suffer from an overlay or dishing problem, portions of dielectric layer 120 overlay into a region 130 otherwise reserved for an air gap due to the insufficient support from underneath barrier layer 100. This overlay problem is particularly notorious in areas of the interconnect structure where metal lines are few and far between or where the distance between successive metal lines is wide. This overlay problem can cause many reliability problems. One such problem is distortion on the surface of the dielectric layer, which would require a planarization process to cure the distortion defect.
Accordingly, what is needed in the art is an air gap interconnect structure and method of manufacture thereof that addresses the above-discussed issues.